Semiconductor integrated circuits are the fundamental building blocks of modern electronic devices. Computers, cellular phones, and consumer electronics rely extensively on these circuits, which may be used for storage of, computations on, and communication of data.
The most common semiconductor devices are formed using silicon as the primary substrate substance. Layers and regions of N-type material (such as elemental silicon), P-type material, and insulative material are combined to form electronic devices and circuits. N-type material is material which includes an excess of electrons, while P-type material is material having an excess of holes. Insulative material is highly resistive to the flow of electrical current and may be used to isolate N and P-type regions.
Silicon technology remains the most widely used in the realization of modern semiconductor devices due, in part, to its widespread availability and low cost. In silicon semiconductor devices, the insulative material usually takes the form of silicon dioxide (SiO.sub.2). N and P-type regions are formed by doped regions of elemental silicon.
Complex electronic components are made by combining and arranging a large number of such semiconductor devices on a single substrate. The devices may be tightly packed into a single package known as an integrated circuit. As an example, a silicon microcomputer chip is an integrated circuit which may include millions of discrete semiconductor transistors and other devices.
In order to form a functional device, the discrete components of a chip package must be selectively interconnected to form a desired circuit. Over the years, aluminum metallization has been the primary vehicle by which interconnection is realized. Typically, metallization involves the deposition of aluminum over the entire silicon substrate. An etching procedure is then carried out to form the desired interconnection pattern.
More recently, titanium disilicide (TiS.sub.2) has been utilized to effectuate contact to device active regions. Titanium disilicide is an attractive metallization material since its properties are advantageous in the manufacturing environment. Among these properties are high temperature stability, low resistivity, compatibility in existing fabrication techniques and excellent contact formation upon silicon regions.
A variety of techniques have been used to deposit titanium disilicide to form contacts on active regions. Included in those techniques are sputtering or evaporation with annealing, and chemical vapor deposition (CVD). A common sputtering and annealing technique is sometimes referred to as the salicide process. This process involves sputtering a blanket layer of titanium followed by annealing, to prevent lateral over-growth of silicide, in nitrogen at less than 700.degree.. The titanium blanket does not react with silicon dioxide regions. Unreacted Ti and TiN are then selectively etched away followed by annealing at temperatures exceeding 750.degree. C.
However, modern trends are toward even more tightly packed, i.e., more densely integrated, circuits. Additional goals include higher speed, lower power consumption, and greater ease of manufacturing. Improving those parameters has turned attention toward making active device regions more shallow. Blanket deposition and etching processes tend to consume underlying silicon in the active device regions and thereby limit the extent of shallowness which may be realized.
A particular sputtering and annealing technique which consumes underlying silicon is the salicide (self aligned silicide) process The salicide process consists of sputtering a layer of Ti metal, annealing in N.sub.2 near 700.degree. C., selectively etching the unreacted Ti and TiN, and then annealing at 750+.degree. C. In the salicide process, all of the silicon for the formation of the titanium disilicide is supplied by the underlying silicon region. Formation occurs because the titanium blanket has a solid phase reaction with the silicon regions. The rate of underlying silicon consumption exceeds the percentage of titanium disilicide formed. Thus, as an example, formation of 2.52 .ANG. layer of titanium disilicide will consume 2.27 .ANG. of underlying silicon. In certain very shallow junction devices, the salicide process will consume too much underlying doped silicon. The doped active regions may form, for instance, the source or drain of a transistor. A CMOS transistor having a channel length of 0.25 .mu.m should have a junction depth in the approximate range of 0.1 to 0.15 .mu.m. Use of the salicide process limits thickness of the titanium disilicide layer to approximately 250 .ANG. for the 0.1 .mu.m junction device, while layers approaching 800 .ANG. are desirable. For these reasons, it is difficult to realize the aforementioned goals relating to the tighter packing of integrated circuits.
Silicon on insulator technology (SOI) also demands minimal consumption. SOI typically involves growth of a thin silicon layer (500 to 1000 .ANG. is common) on an insulator, such as silicon dioxide. Forming contacts with the silicon layer requires minimal consumption because of the thinness of the silicon layer.
Chemical vapor deposition techniques have also been investigated as possible methods for production of titanium disilicide layers. However, effectiveness of the techniques has been limited.
For a viable production using CVD, a number of critical parameters must be met simultaneously during growth. One such parameter is selectivity. Selectivity refers to the ability to limit titanium disilicide growth to the silicon regions. In a large scale commercial manufacturing environment, an effective deposition technique requires 100% selectivity, referring to the case where all growth is on silicon regions and no titanium disilicide forms on the silicon dioxide regions. Additionally, growth temperatures should be low enough to prevent redistribution of dopants in the silicon regions. Temperatures exceeding 750.degree.-800.degree. C. tend to allow high levels of dopant distribution.
Thickness of the titanium disilicide layer is also important. Typical integrated circuits utilize a thickness approaching 800 .ANG.. With the device dimensions discussed above, the consumption of silicon should therefore be less than approximately 10%. Growth rates should also exceed approximately 1000 .ANG. per minute to achieve economical wafer production. Finally, morphology of the substance must be good.
In sum, there is a need for a commercially viable selective chemical vapor deposition technique which will allow contacts to be formed on the increasingly compact and shallow silicon semiconductor devices, and which consumes minimal silicon from a silicon substrate while forming with 100% selectivity only on regions of silicon.
It is therefore an object of the present invention to provide an efficient process that exhibits 100% selectivity for commercially viable selective chemical vapor deposition of titanium disilicide onto a silicon substrate including silicon regions and silicon dioxide regions.
Another object of the present invention is to provide an efficient process for commercially viable selective chemical vapor deposition of titanium disilicide onto a silicon substrate which allows for the formation of sufficiently thick contacts, even with very shallow junction devices.
Still another object of the invention is to provide an efficient process for commercially viable selective chemical vapor deposition of titanium disilicide onto a silicon substrate which is conducted at a low temperature where dopant diffusion is negligible.
A further object of the invention is to provide a commercially viable selective chemical vapor deposition process that minimally consumes underlying silicon in the silicon regions and is applicable to silicon on insulator technology.